Semiconductor chips are known whose electrical connections are all arranged on the underside, via which the semiconductor chips are mounted on a substrate. By way of example, light-emitting semiconductor chips are known which can be electrically connected via electrical connection regions on only one side. On account of the customary manner of production and subsequent mounting, which involves applying the connection regions on the top side of semiconductor layer sequences which have already been produced beforehand, said top side then subsequently being used as the underside for mounting on a carrier, such semiconductor chips are also designated as so-called “flip-chips.”
Semiconductor chips of this type afford the advantage that, for example, wire contacts, for instance in the form of so-called bonding wires, are no longer necessary for the electrical connection.
Specifically in the case of so-called “power chips,” which are preferably operated with high currents, it is advantageous to solder the chips onto a substrate for good dissipation of heat. One characteristic property of soldering connections is the high mechanical stiffness. In order to avoid damage to the semiconductor chip or the mounting connection of the chip, materials having a coefficient of thermal expansion (CTE) adapted to the semiconductor chip are preferably used as substrate materials. Such an approach leads to a good reliability of the interface between the semiconductor chip and the substrate. In the case of an adapted CTE, meaning in particular an identical or at least comparable CTE, only low mechanical stresses are built up between the semiconductor chip and the substrate. Even under cyclic thermomechanical loading, a good reliability can thus be achieved since the mechanical stresses caused by a CTE mismatch, that is to say a difference in the coefficients of thermal expansion, can be minimized.
However, this approach has the disadvantage that it is necessary to find suitable substrate materials which have a CTE adapted to the CTE of a semiconductor chip and are electrically insulating and have good thermal conductivity. The customary substrate materials for light-emitting semiconductor chips have a CTE in the range of between 4 and 6 ppm/kelvin. They are often combined with ceramic printed circuit boards as substrates, for example, composed of aluminum oxide or aluminum nitride, wherein for example the CTE of AN is in the range of 6 to 7 ppm/kelvin. However, such a material has the disadvantage that it is very expensive.
If the substrate is furthermore formed with a large area, that is to say has a geometrically larger extent than the semiconductor chip, the CTE mismatch problem is shifted from the interface between the semiconductor chip and the substrate to the interface between the substrate and a mounting area on which the substrate is arranged. The mounting area consists very generally of metal and is usually larger than the chip-substrate interface by a multiple. Therefore, the CTE mismatch at least at the interface between the substrate and the mounting area is likewise problematic.
Furthermore, ceramic substrate materials such as, for example, aluminum oxide or aluminum nitride are suitable only to a limited extent for use in relatively large modules. The low ductility of these materials can result in mechanical problems such as panel fracture, for instance. As a result of the high costs for example when using aluminum nitride, the production costs are increased and economic viability is thus jeopardized.
As an alternative, metal core printed circuit boards are appropriate, for example. These materials comprise a metal plate, for example composed of aluminum, which is coated with a dielectric. The actual interconnection plane with the chip mounting areas is applied on the surface of the dielectric. However, metal core printed circuit boards (MCPCB) have a CTE of usually approximately 23 ppm/kelvin in the case of aluminum as the metal core. Therefore, the CTE of such an MCPCB is greater than the CTE of customary semiconductor chip materials by approximately a factor of four. In the case of loads arising from thermal cycling, forces which can lead to the failure of the weakest element are built up as a result of this CTE mismatch. For the case where only low power losses have to be dissipated, it is also possible to use FR4 materials as the substrate, which typically have a coefficient of thermal expansion of 16 ppm/kelvin. In all these cases, however, the CTEs of semiconductor chip and substrate do not match. In the case of loading arising from thermal cycling, forces are built up which can lead to damage to the semiconductor chip and/or the interface or connection between the semiconductor chip and the substrate.
In order to be able to solve this problem, it is also known to link a semiconductor chip to a substrate having a different CTE by means of an elastic connection. In the case of this approach, mounting is effected by means of an organic material, for example, a conductive adhesive, the materials of which enable an elastic deformation of the interface between the semiconductor chip and the substrate. As a result, although mechanical forces can be buffered, typical conductive adhesives have a low thermal conductivity of usually approximately 1.8 W/m·K, with the result that the heat loss which can arise during the operation of customary semiconductor chips cannot be effectively dissipated.
As an alternative thereto, it is also possible to make contact with semiconductor chips by means of a so-called “solder bump array” in a manner comparable to the technique such as is used when constructing so-called “ball grid array” components. In the case of this approach, a mechanical flexibility of the interface between semiconductor chip and substrate is achieved by the metallization being divided among many small soldering locations. However, this does not enable a semiconductor chip to be areally linked to a substrate. The necessary distance between the solder bumps results in considerable losses in the linking area. The dissipation of the heat loss by this linking is significantly poorer compared with an areal linking.